1. Field of the Invention
The present invention relates to a method of storing data in a memory of a data processing system, which memory comprises a plurality of memory blocks. The method has particular, but not exclusive, application to image processing. The present invention also relates to a data processing system for the application of said method.
2. Description of the Prior Art
In image processing systems a scene is scanned and information, for example image contrast information, concerning an aspect of the scene is stored for further processing. The processing may (or may not) be carried out in real time. The scanning may be done in a sequential manner or a pseudo-random manner. Also the speed of scanning of a scene depends on whether or not there is movement and, if there is, the speed of movement of the object(s) of interest.
When scanning a scene, elements of a scene of an arbitrary predetermined size, generally termed pixels, are normally stored in a semiconductor frame store. One characteristic of the frame store is that the system must be able to write-in and read-out information relating to a pixel at a certain speed, the whole read/write cycle taking place at frame rates.
An important parameter concerning semiconductor memories is access time, that is, the time period to address a location in a store and read-out or write-in the information to be stored. In the case of scanning a scene at video speeds, the access time would be of the order of tens or a few hundreds of nanoseconds which means either an expensive high speed frame store has to be provided or steps are taken to achieve the desired access time using cheaper low speed stores. One method of using low speed devices is to have a low speed main memory comprising a plurality of small high speed parallel arranged blocks or stages each of which has a buffer. The blocks are multiplexed so that each one is addressed in sequence at frame speeds and the information to be stored at the addressed location is held temporarily in the high speed buffer and is read-out to the addressed block location during the remainder of the period of that multiplex cycle. Thus by way of example if a frame store comprises 16 blocks with associated high speed buffers and each block has a maximum capacity of 32.times.512 pixels, then in order to scan an entire frame in 20 mS, each location has to be addressed in (20.times.10.sup.-3)/(512.times.512) sec or 76 nS. This means that the high speed buffer has to accessible in 76 nS, however, since there are 16 blocks then the high speed buffer can dump the information into its associated block in 16.times.76 nS=1.216 .mu.S before having to be ready to receive the information relating to the next pixel to be stored in that block.
This multiplexing approach is satisfactory if the frame is scanned at a frequency and in a sequence which permits each storage location to read-out and write-in information within its maximum time. However, conflicts will occur when the scanning pattern is such that it may be necessary to address any one of the 16 low speed blocks two or more times in one cycle or when it is desired to operate the block above its maximum access speed. One way of resolving this problem is to provide additional buffers. However this is not a satisfactory solution since the buffers may become depleted by successive reads and overfilled by successive writes.
It is an object of this invention to overcome this problem.